
COMMERCIALTEMPERATURERANGE
16
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PCI STOP FUNCTIONALITY
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF[1:0] and SRC clocks can be set to be free-running through SMBus
programming, they will ignore both the PCI_STOP# pin and the PCI_STOP register bit.
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[1:0]
clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at IREF * 6 (or
tristate if Byte 5 Bit 7 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
PCI_STOP# - DE-ASSERTION
Thede-assertionofthePCI_STOP#signalistobesampledontherisingedgeofthePCIFfreerunningclockdomain.AfterdetectingPCI_STOP#de-assertion,
all PCI[6:0], stoppable PCIF[1:0] and stoppable SRC clocks will resume in a glitch free manner.
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
tSU
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
tSU
tDRIVE_SRC
PCI_STOP#
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
DOT96
DOT96#
REF
1
Normal
33MHz
48MHz
Normal
14.318MHz
0
Normal
IREF * 6 or float
Low
48MHz
Normal
14.318MHz